In Dynamic Random Access Memory (DRAM) systems, both hard and soft errors may occur in the bits of the DRAM. Hard errors corrupt bits in a repeatable manner and concern physical damage to the memory cells whereas soft errors comprise random corrupt bits that may be corrected using an error correction algorithm and parity data for the cache line including a defective bit.
To avoid hard errors, sparing techniques may be used to replace sections of the memory dies having the errors with other spare memory dies not having errors. With row sparing, if a manufacturer or operating system during operations discovers a row of the DRAM having a defect (one or more defective bits), a fuse in the DRAM may be blown to map a spare row into the array to replace the defective row and map the defective row out of the memory array.
A rank sparing technique may replace a rank of DRAM devices, i.e., the physical chips, having a hard error with a spare rank on the DRAM. A memory rank is a set of DRAM chips connected to the same chip select signal that are accessed simultaneously and share command and control signals.
There is a need in the art for improved sparing techniques.